1. Field of the Invention
The present invention relates to a method of assembling a semiconductor device, and more specifically to a method of assembling a semiconductor device forming an encapsulant.
2. Description of the Related Art
Referring to FIG. 1A, a plurality of semiconductor devices fabricated using conventional flip chip technology are shown. Substrate 100a has a plurality of packaging units 112a for assembling a plurality of the semiconductor devices. In FIG. 1A, as the name implies, flip chip technology is characterized by flipping over a semiconductor chip 10a for attachment to a substrate, through conductive bumps 12a. However, as is known, significant strain is imposed on the conductive bumps 12a during temperature cycling, when an organic material is used as the substrate. This strain results from the significant difference between the coefficient of thermal expansion between the organic substrate (14-17 ppm/xc2x0 C.) and the silicon wafer (4 ppm/xc2x0 C.). Consequently, the conductive bumps 12a deteriorate over time at an accelerated rate.
Therefore, to reduce this connection strain and enhance reliability, encapsulant 120a is usually filled into the space between the substrate 100a and the semiconductor chip 10a. In this way, stress is dispersed to the encapsulant to alleviate stress on the conductive bumps 12a. Thus, connection cracking is significantly reduced, and the life of the conductive bumps 12a is prolonged. In addition, the encapsulant 120a also prevents the transmission of leakage current caused by impurities between the conductive bumps 12a. Statistical data shows that the reliability of the device can be increased five to ten times when underfill encapsulation is utilized. Therefore, underfill encapsulation has become a highly important process. However, there are problems that arise in connection with the various ways of performing the underfilling process.
Conventionally, most flip chip packages are encapsulated by dispensing a liquid encapsulant with low viscosity along the periphery of the chip. Capillary action, generated from the encapsulant in the narrow space between the chip and the substrate, drives the encapsulant to fill the gap between the solder connections. Since filling is conducted by capillary action, it is very slow. For example, in a typical encapsulation operation, the filling takes several minutes to several tens of minutes depending on the filling temperature and chip size. Further, one encapsulating apparatus can only encapsulate a single chip in one run dispensing a liquid encapsulant with low viscosity along the periphery of the chip. The throughput per encapsulating apparatus is very low. Many encapsulating apparatuses are therefore necessary for mass production, negatively affecting the production cost. Furthermore, since capillary action alone is insufficient to fill all the space between the chip and the substrate, voids are easily formed in the encapsulant. Such voids require the flip chip package to be discarded from either popcorn effect, caused during subsequent thermal processes, or stress concentration, caused when the flip chip package is stressed.
Referring to FIG. 1B, a plurality of semiconductor devices fabricated using conventional wire-bonding technology are shown. Substrate 100b has a plurality of packaging units 112b for assembling a plurality of the semiconductor devices. Semiconductor chips 10b are respectively attached to packaging units 112b and connect to substrate 100b using wires 12b. Semiconductor chips 10b and wires 12b are covered by a molding compound 120b. Further, another package type, tape automatic bonding (TAB), may be produced when a substrate with a plurality of pre-formed leads (not shown) is used rather than the substrate 100b and wires 12b. 
When the semiconductor devices fabricated using conventional wire-bonding or TAB technology are encapsulated using a liquid encapsulant, a plurality of semiconductor devices can be encapsulated at the same time, but voids are still easily formed in the encapsulant.
Referring to FIG. 1C, a plurality of semiconductor devices of multi-chip module (MCM) type fabricated using stacked-die technology are shown. Substrate 100c has a plurality of packaging units 112c for assembling a plurality of the semiconductor devices. Semiconductor chips 10c are respectively attached to every packaging unit 112c and electrically connect to substrate 100c through conductive bumps 12c. Semiconductor chips 10d are respectively attached to and stacked overlying each semiconductor device 10c and electrically connect to substrate 100c through wires 12d. Spaces between the substrate 100c and semiconductor chips 10c are filled by underfill 120c. Semiconductor chips 10d, wires 12d, and underfill 120c are covered using a molding compound 120d. Further, a substrate with both flip chip and TAB type (not shown) may be provided rather than the substrate 100c, using a plurality of leads (not shown) electrically connecting the substrate and semiconductor chips 10d. 
The semiconductor device of MCM type shown in FIG. 1C faces challenges in process complexity, process yield, and product reliability resulting from using a plurality of assembling technologies such as flip chip, wire-bonding, and TAB. The aforementioned problems in flip chip package, wire-bonding package, and TAB package will occur at the same time when fabricating the semiconductor device of MCM type. Compared to the semiconductor device fabricated using other assembling technologies, there is further an interface between the underfill 120c and molding compound 120d, a negative factor affecting the process yield and product reliability of the semiconductor device of MCM type.
Solutions for the void in the encapsulant of the semiconductor device have been disclosed. U.S. Pat. Nos. 5,834,339 and 6,107,123 respectively disclose a method characterized as sealing a gap between a chip and a substrate with a fluid, curable encapsulant using the application of a uniform pressure such as an isostatic or hydrostatic pressure thereto for removal of voids and gas bubbles in the encapsulant. However, the encapsulant is still provided by dispensing, so encapsulating cycle time cannot be improved. Further, an extra tooling is necessary to control the encapsulant flow when applying the uniform pressure, negatively affecting the production cost. Furthermore, the method can only be used in the underfill process. U.S. Pat. No. 6,000,924 discloses a method and device providing a special mold to surround a chip to be encapsulated in a cavity, with an encapsulant injected into the cavity at an elevated pressure, and possibly at an elevated temperature. However, the mold must be specially designed to match the size of the chip to be encapsulated, negatively affecting production cost. Further, the mold still can only encapsulate a single chip in one run, thus the throughput of the mold is not improved. U.S. Pat. No. 6,187,613 discloses a process placing a metal foil on a flip chip that has been connected to a substrate, then applying downward pressure to the metal foil so as to form space between the metal foil, flip chip, and substrate, and filling an encapsulant into the space under pressure. The metal foil is about 0.01 mm to 0.1 mm thick and can withstand an encapsulating pressure exceeding 100 psi. However, the encapsulant is still provided by dispensing, so encapsulating cycle time cannot be improved. Further, the metal foil is very expensive and may be deformed under pressure, negatively affecting the uniformity of the sizes of the encapsulated flip chips. Furthermore, the process still can only encapsulate a single chip in one run, thus the throughput is not improved.
U.S. Pat. No. 6,046,076 discloses a method of encapsulating a microelectronic assembly applying a flowable encapsulant to the assembly while maintaining the assembly at sub-atmospheric pressure, then bringing the assembly to a higher pressure after completion of the encapsulant-applying step and holding the assembly at the higher pressure, and curing the encapsulant after bring the assembly to the higher pressure. However, the encapsulant is still provided by dispensing, so encapsulating cycle time cannot be improved. Further, the dispensing volume of the encapsulant must be exactly controlled, or the encapsulant can flood the apparatus. Although a mold chest specially matching the size of the assembly can be provided for preventing encapsulant flooding, the production cost is negatively affected. U.S. Pat. No. 6,255,142 discloses a method and apparatus providing a removable seal to encapsulate a semiconductor device therein. The method further provides a pressure differential to fill an encapsulant in a gap between the semiconductor device and a substrate used therewith. The pressure differential is formed using a vacuum source. However, the encapsulant is still provided by dispensing, so encapsulating cycle time cannot be improved. Further, the gap cannot be completely filled only using the pressure differential. Furthermore, the application of the removable seal is not suitable for mass production. U.S. Pat. No. 6,255,142 discloses a method including evacuating a first chamber, placing a semiconductor chip package into a second chamber at atmosphere, evacuating the second chamber and moving the semiconductor chip package to the evacuated first chamber, dispensing an encapsulant material about the periphery of the semiconductor chip package in the evacuated first chamber, evacuating a third chamber, transporting the encapsulated semiconductor chip package from the first chamber into the evacuated third chamber, and vending the third chamber to atmosphere to force the encapsulant material into the semiconductor chip package. However, the encapsulant is still provided by dispensing, so encapsulating cycle time cannot be improved. Further, when a plurality of semiconductor chip packages is encapsulated at the same time using this method, not only is throughput low, but the encapsulating procedure is slow and complicated. Furthermore, the encapsulant cannot completely fill the gap between the semiconductor chip and substrate of the semiconductor chip package at atmosphere.
As mentioned, none of the aforementioned disclosures perfectly meet the requirements of encapsulating a plurality of semiconductor devices at the same time, preventing voids in the semiconductor devices, completely covering the semiconductor chip specifically for encapsulating the semiconductor device (underfill) of flip chip type, and sustaining compatibility with all assembly technologies, such as flip chip, wire-bonding, TAB, and others.
Thus, objects of the present invention are to provide a method of assembling a semiconductor device forming an encapsulant, the method allowing a plurality of semiconductor devices to be encapsulated at the same time, preventing voids in the semiconductor device, completely covering the chip when encapsulating the semiconductor device, specifically with flip-chip semiconductor devices, the method further supporting compatibility with all assembly technologies, such as flip chip, wire-bonding, TAB, and others, thereby improving production yield, reliability, lifetime, and throughput of the semiconductor device, and reducing the cost of encapsulating apparatus.
In order to achieve the exceeding objects, the present invention provides a method of assembling a semiconductor device forming an encapsulant. First, a substrate, having a plurality of semiconductor devices, respectively having a semiconductor chip electrically connected to a predetermined encapsulation area on a surface of the substrate is provided. Next, an encapsulant is filled overlying the predetermined encapsulation area using stencil printing, sweeping excess encapsulant over the predetermined encapsulation area at a first air pressure less than approximately 1 atm. Further, encapsulant overlying the predetermined encapsulation area is swept over the predetermined encapsulation area using stencil printing at a second air pressure exceeding the first air pressure. Finally, the encapsulant is hardened at a third air pressure exceeding approximately 1 atm.